Formal VLSI correctness verification : proceedings of the IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design
Ifip Wg, Luc Claesen · Medical Entomology and Zoology · 1990
MOS Circuit Level Verification. Efficient Tautology Checking Algorithms. Verification of Sequential Machines. Functionality Extraction, Comparison and Testing. Register Transfer Level Verification. Boyer-Moore Theorem Prover Based Verification. Hardware Verification Using HOL.