Applications of testability analysis: from ATPG to critical delay path tracing
F. Brglez, Philip Pownall, Robert Hum · International Test Conference · 1984
This contribution outlines the applications of a recently proposed analysis algorithm that has been implemented as a controllability/ observability program named COP. Several benchmark modules, some approaching the complexity of VLSI, established that CPU cost grows only linearly with the size of the modules in all of the applications considered to date. These include effective heuristics for automatic test pattern generation (ATPG), assessment of random pattern testability, effective approach to approximate fault simulation. structural partitioning into cones, critical delay path tracing and characterization of the module in terms of a testability signature. In view of the increasing complexity of VLSI, such performance provides strong motivation that the calibration of analysis be enhanced and its role further expanded.