Vlsi Prolog Processor, Design and Methodology : A Case Study in High Level Language Processor Design
Pierluigi Civera, Guido Masera, Gianluca Piccinini, Maurizio Zamboni · Medical Entomology and Zoology · 1994
Part 1 The Prolog Paradigm: What is Prolog? The origin. Facts. Goals. Logic variables. Rules. Recursive programming. Lists and structures. Pure Prolog and built-in predicates. Metalogical predicates. Extra-logical predicates. An example. Prolog as a General Theorem Prover. Future Applications. Prolog Execution. Part 2 The Sequential Execution Models for Prolog: Prolog Language Implementations: a Brief History. Interpreting Prolog. Compiling Prolog: the Warren Abstract Machine. The Problems of Prolog Execution. Part 3 The Parallel Execution Models for Prolog: An Analysis of the Intrinsic Parallelism of Prolog. Where and When the Parallelism Can Be Effective. The Implemented WAM Parallel Models. SRI model. Argonne model. SICS VVWAM model. Berkeley PPP model. RAP-WAM model. Part 4 VLSI Prolog Machines: The Japanese FGCS Experience. The Berkeley PLM Machine. The PROXIMA Prolog Machine. Other Proposals. Part 5 Methodology for High-Level Language Architectures: Mapping a HLL Languages on a VLSI Circuit. Partitioning. Instruction Set and Abstract Machine. Simulation and Analysis of the Abstract Machine. Hardware Considerations. System Architecture. Processor Organization. The High Level Synthesis. Part 6 Prolog Architectural Requirements: Analysis of the Computational Model. Data Structure and Instruction Requirements. Microarchitectural Requirements. What is Missing in a General Purpose CPU. The PROXIMA Prolog Processor: a Case Study. Design Decisions. Development Tools for Simulations. Microarchitecture. Description. Data path. Control unit. The prefetching unit. Instruction format. Part 8 PROXIMA VLSI Implementation: VLSI Technological Constraints. CAD Tools. Silicon Compilation. Microarchitecture Design and VLSI Implementation. Partitioning. The processor. The prefetcher unit.