Agp System Architecture
Dave Dzatko, Tom Shanley · Medical Entomology and Zoology · 1999
From the Book: About This Book The MindShare Architecture Series The MindShare Architecture book series includes: ISA System Architecture, EISA System Architecture, 80486 System Architecture, PCI System Architecture, Pentium System Architecture, PCMCIA System Architecture, PowerPC System Architecture, Plug-and-Play System Architecture, CardBus System Architecture, Protected Mode Software Architecture, Pentium Pro and Pentium II System Architecture, USB System Architecture, FireWire System Architecture and AGP System Architecture. The book series is published by Addison-Wesley. Rather than duplicating common information in each book, the series uses the building-block approach. ISA System Architecture is the core book upon which the others build. Cautionary Note The reader should keep in mind that MindShare's book series often deals with rapidly-evolving technologies. This being the case, it should be recognized that the book is a snapshot of the state of the targeted technology at the time that the book was completed. We attempt to update each book on a timely basis to reflect changes in the targeted technology, but, due to various factors (waiting for the next version of the spec to be frozen, the time necessary to make the changes, and the time to produce the books and get them out to the distribution channels), there will always be a delay. Organization of This Book The book is organized as follows: Chapter 1: describes some of the motivating factors for the creation of the Accelerated Graphics Port (AGP). Some of the limitations of PCI graphics are discussed in the context of rendering a 3-D image. Chapter 2: introduces AGP with a description of themajorfeatures and a discussion of some of the fundamental system requirements to support the interface. A basic overview of AGP technology can be gained from this chapter. Chapter 3: outlines the major signaling requirements of the AGP interface. The electrical AC and DC specifications are described. AGP driver and receiver characteristics are presented. Chapter 4: defines the required and optional signals for AGP-compliant masters and targets. The signals are grouped by function and the purpose of each signal is described. Chapter 5: focuses on the arbiter's role within the AGP interface. Optimization of grant pipelining is also discussed. Chapter 6: defines all of the AGP commands, or transaction request types, that can be issued on the AGP bus. The rules associated with the ordering of these transactions by the core logic are explained through the use of examples. Chapter 7: AGP transactions are broken into two distinct bus operations: the issuance of the transaction request by the AGP graphics accelerator (referred to as the AGP master), and the matching data transaction that is initiated later in time by the core logic (referred to as the AGP target). This chapter provides a detailed description of the issuance of transaction requests using the AD and C/BE busses, as well as the SBA port. Chapter 8: There are two categories of transactions that can be performed on the AGP bus: AGP transactions and PCI transactions. This chapter explores the differences between the two. Chapter 9: provides a detailed description of AGP data transactions in 1X, 2X, and 4X data transfer modes. Chapter 10: provides a detailed description of Fast Write transactions in the 1X, 2X, and 4X data transfer modes. Chapter 11: describes issues related to add-in cards, connectors, and the motherboard. Chapter 12: describes the responsibilities of the software required for initializing and configuring AGP devices. The AGP-specific configuration registers used in the configuration process are described. Who This Book Is For This book is intended for use by hardware and software design and support personnel. Due to the clear, concise explanatory methods used to describe each subject, personnel outside of the design field may also find the text useful. Prerequisite Knowledge The reader should be familiar with PC and PCI System Architectures. MindShare's ISA System Architecture and PCI System Architecture books provide that foundation material. Documentation Conventions This document contains conventions for numeric values as follows: Hexadecimal Notation This section defines the typographical convention used throughout this book. Hex Notation All hex numbers are followed by an h. Examples: 9A4Eh 0100h Binary Notation All binary numbers are followed by a b. Examples: 0001 0101b 01b Decimal Notation Numbers without any suffix are decimal. When required for clarity, decimal numbers are followed by a d. The following examples each represent a decimal number: 16 255 256d 128d Bits versus Byte Notation This book employs the standard notation for differentiating versus bytes. All abbreviations for bits use lower case. For example: 1.5Mb/s 2Mb All references to bytes are specified in upper case. For example: 10MB/s 1KB Identification of Bit Fields (logical groups of or signals) All bit fields are designated in little-endian bit ordering: [X::Y], where X is the most-significant bit and Y is the least-significant bit of the field. Author Biography: David Dzatko has over ten years of experience designing and testing computer systems. He is currently an instructor with MindShare, Inc., teaching computer architecture to leading companies in the computer industry