Reconfigurable Implementation for the AES Algorithm
Raoel Ashruf, Georgi Gaydadjiev, Stamatis Vassiliadis · 2002
The choice of a platform, software, ASIC or FPGA, is driven by several aspects, such as algorithm performance, cost and flexibility. Although ASIC has the highest performance and the lowest unit cost, it has no flexibility at all. While software has the most flexibility of all, the performance is very low. The MOLEN architecture, developed at the Techinical University of Delft, open up new perspective for this problem. The architecture is based on a cooperation between a general purpose core processor and reconfigurable hardware, for example a FPGA. Since cryptographic algorithms are relative frequently upgraded, this high flexibility is desperately needed. There are several reasons for upgrading such as when the algorithm is broken or there is a better algorithm or even in case where an algorithm independent protocol is needed. To put it briefly the -coded processor put a new perspective on great performance and high flexibility. In this paper we investigate several Rijndael (AES) implementations based on the Molen -coded processor. Two types of FPGAs, Xilinx and Altera, are evaluated in order to produce realistic results. In addition, a modified simulator based on the SimpleScalar Toolset (v3.0)is used to estimate the performance potential. The profiling of the AES code is done based on different methodologies. In this paper an analogy is drawn between. The VHDL descriptions produced, are enhanced with standard interface making them reusable for other research projects based on the same architecture and dealing with similar data processing problems. The AES running on the top of Molen performs equaly good as other FPGA based solutions. The main advantage of our solution is that reconfiguration from one keysize to another is done faster than on pure FPGA implement...