Vhdl: A Logic Synthesis Approach
D. Naylor, Simon Jones · 1997
From the Publisher: VHDL has become one of the important tools used in the design of electronic circuits and systems. It allows complex designs to be developed more rapidly and reliably than before and is becoming a standard in more and more companies as well as in university courses. A major feature of the language is in its use to write CAD tools known as logic synthesizers to produce the circuit design from high-level descriptions of the required function of the circuit. The use of VHDL for constructing these logic synthesizers is one of the twin aims of the book; the second is the application of the tools to the design process. Since logic synthesis offers enormous gains in productivity, all circuit designers will need to be familiar with its use. VHDL: A Logic Synthesis Approach is specifically targeted at this audience and is also essential reading for engineers wishing to use the more basic manual VHDL techniques. The book is structured in a practical, example-driven manner. The constructs of VHDL are introduced as and when the examples need them. Worked examples, questions and answers are provided together with dos and don'ts of good practice. An appendix on logic design is included and the source code is available free of charge over the Internet.