Reducing FPGA Reconfiguration Time Overhead using Virtual Configurations
Ming Liu, Zhonghai Lu, W. Kuehn, Axel Jantsch · 2010
Abstract—Reconfiguration time overhead is a critical factor in determining the system performance of FPGA dynamically reconfigurable designs. To reduce the reconfiguration overhead, the most straightforward way is to increase the reconfiguration throughput, as many previous contributions did. In addition to shortening FPGA reconfiguration time, we introduce a new concept of Virtual ConFigurations (VCF) in this paper, hiding dynamic reconfiguration time in the background to reduce the overhead. Experimental results demonstrate up to 29.9% throughput enhancement by adopting two VCFs in a consumerreconfigurable design. The packet latency performance is also largely improved by extending the channel saturation to a higher packet injection rate. I.