Pipelined bit-slice architecture eases FFT implementation
J. Duval, Jeff Niehaus · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1983
For large arrays, fast fourier transforms (FFTs) prove superior to discrete fourier transforms (DFTs), but still too computation-intensive for general-purpose, real-time processors. A pipelined bit-slice array processor has an architecture suited for real-time FFTs. The Sn54/74As888, a 20-mhz bipolar 8-bit slice that's scheduled for 1st quarter sampling, provides several features that suit it particularly well for ffts; these features include pipelined instruction prefetch, an alu-bypass scheme that speeds multiplication and division, a 3-operand register file with three I/O paths and internal shift multiplexers that eliminate external shift-control parts. 3 references.