A Multi-Core Approach to Addressing the Energy-Complexity Problem in Microprocessors
Rakesh Kumar, Keith I. Farkas, Norman Paul Jouppi, Partha Ranganathan, Dean Michael Tullsen · 2003
This paper proposes single-ISA heterogeneous multicore architectures as a mechanism to reduce processor power dissipation. It assumes a single chip containing a diverse set of cores that target different performance levels and consume different levels of power. During an application’s execution, system software evaluates the resources required by an application for good performance and dynamically chooses the core that can best meet these requirements while minimizing energy consumption. It describes an example architecture with five cores of varying performance and complexity. Initial results show a more than three-fold reduction in energy at a cost of only 18 % performance. 1