Two Methods for Synthesizing VHDL Concurrent Processes
Petru Eles, Krzysztof Kuchciński, Zebo Peng, Marius Minea · 2007
This paper presents two methods for high-level synthesis of VHDL specifications containing concurrent processes, that were implemented in the CAMAD high-level synthesis system. Our synthesis subset, called S'VHDL, accepts a large subset of standard VHDL including the concurrent features of the language. A primary concern was to preserve simulation/synthesis correspondence during synthesis and to produce hardware that operates at high performance with low complexity. One of the main difficulties lies in the fact that signal assignment semantics is defined in standard VHDL in terms of the simulation cycle. We first developed a method that allows a practically unrestricted use of signals and wait statements, by producing a synchronous hardware with a global control of process synchronization for signal update. The resulted hardware can be controlled either by a single state machine or by a collection of FSMs working synchronously together. The second method allows hardware sy...