A technique for making asynchronous sequential circuits readily testable
Alfred K. Susskind · International Test Conference · 1984
A design technique for making asynchronous (unclocked) sequential circuits easily testable is given. Through the addition of (1) one or at most two state variables; (2) one input lead; and (3) the use of one or more observable output leads, we achieve scan-out and also make the given machine strongly connected. Verification of proper operation can then proceed as in classical machine identification previously restricted to synchronous designs. An example of the implementation of our technique is given for the case where the 1-out-of-n state assignment is used.