Algorithm/Architecture Co-Design of a Picture-Rate Up-conversion Module.
Aleksandar Beric, Ramanathan Sethuraman, Jef van Meerbergen, Geert de Haan · 2002
Abstract — De-interlacing is a major determinant of image quality in a modern display processing chain. The de-interlacing method based on the generalized sampling theorem (GST) applied to motion estimation and motion compensation provides the best de-interlacing results. With HDTV interlaced input material (1920*1080i), this method requires about 1000 GOPs and a communication bandwidth around 10 Gbytes/sec. We analyze and simplify the algorithm and propose a processing architecture. As a result, the operation count of the motion estimator decreases with a factor of 5.5 and the bandwidth to local pixel storage with a factor of 3.3 with only mild and acceptable quality loss. We present a task breakup and a suitable heterogeneous multi-processor architecture. The task break-up is such that the computational load of the processors is balanced and the flexibility of the architecture is preserved within the application domain. To cope with the large memory bandwidth requirements, we exploit locality of reference with multi-level scratchpad memories. I.