System Design Methodology and Tools
Daniel D. Gajski, Junyu Peng, Andreas Gerstlauer, Haobo Yu, Dongwan Shin, Daniel D. Gajski · 2003
this report. 28 Simulation Approach System RTL Logic Transistor VHDL, Verilog, Copyright 2002 Daniel D. Gajski Simulation approach focuses design methodology on simulation. Designers develop design on different levels and simulate its behavior by writing simulation models. Formal verification or equivalence checking is almost impossible since simulation models are ambiguous and not strict enough for synthesis and verification. Usually, simulation model must be restricted to a language subset or a particular style to be synthesizable and even more restricted to be verifiable. This simulation approach reverses the trend established by logic synthesis where design methodology focuses on synthesis while creating simulatable models automatically