High-speed lookup table technique for digital multiplication
J.E. Simpson, R.A. Wayne · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1978
The development of a 12-bit, fixed-point tabular multiplier for use in real-time digital processing is discussed. Standard iterative multiplying processes are too slow, and hardware multiplying arrays which provide the required speed are too complex and have too many components. This tabular approach uses answer pointers and compressed answer tables which can be implemented with standard RAM or with special ROM-supported devices. This reduces the required digital hardware by at least half and thus improves the critical power budget, package size, and reliability of the signal processor.