Rapid Prototyping & Evaluation of High-Performance Computers
Rich Brown, John Hayes, Trevor Mudge · 1996
This report discusses our work with an emulator based on f ield programmable gate array technology. This technology has made possible the construction of hardware emulators capable of emulating systems having a million gates at clock speeds of 1 MHz and more. Thus it is now possible to run realistic workloads on prospective designs and measure the results. There are three areas that these new emulators can be applied to: 1) validation; 2) concurrent hardware and software development; and 3) rapid prototyping of design alternatives. The report outlines the technology of emulators discussing strengths and weaknesses. It discusses our experiments with a second generation emulator. Concluding remarks address the future potential of this technology.