Inter-process Communications for System-Level Design
Paolo Enrico Camurati, Fulvio Corno, P. Prinetto, C. Bayol, B. Soulas · 1996
Working at system level is attracting increasing interest, as it supports the exploration of several alternatives, before the hardware/software partitioning takes place. New issues must be taken into account, such as validation and verification at all steps. Within the framework of a system-level design methodology that supports verification, communication protocols among processes play a key role. Protocols are presented that cover most relevant aspects useful in system-level, verifiable designs, together with the design for verifiability rules they entail both on the design methodology and on the use of VHDL as a description formalism. 1. Introduction The boundaries of hardware description are rapidly migrating towards higher and higher levels of abstraction. Until not long ago, designers mainly worked at register-transfer level, whereas new activities at system-level are now emerging. Systems are conceived before partitioning between hardware and software realization takes place, so...