Fault models and tests for two-port memories
A.J. van de Goor, Said Hamdioui · 2002
In this paper the effects of simultaneous memory access on the fault modeling for two-port memories are investigated. New fault models and their march tests are presented. The obtained tests are of order O(n/sup 2/), which makes them less practical for larger two-port memories. However, the complexity can be reduced to O(n), when the memory topology is taken into account.