Design Trade-Offs in M–C and R–C Delay Architectures for Secure and Scalable Arbiter PUFs
V Madeshvaradhan, Aman Kumar Singh, Marco Luigi Ottavi, Vishal Gupta · 2025
As IoT devices become increasingly interconnected and resource-constrained, hardware-level security is essential. Physically unclonable functions (PUFs) offer a lightweight, tamper-evident solution for secure authentication and key generation. Among them, the Arbiter PUF stands out for its simplicity and scalability, utilizing delay differences in identically structured paths. Traditionally, these delays are generated using resistor-capacitor (RC) circuits, but they suffer from static resistance, limited tunability, and higher power consumption. To overcome these limitations, this work proposes a memristor-capacitor (MC) based Arbiter PUF. Memristors provide tunable resistance, non-volatility, and inherent variability, enhancing both entropy and adaptability in PUF architectures. Our analysis demonstrates that replacing resistors with memristors in delay elements significantly enhances the key performance metrics of the PUF. Simulation results reveal improved uniqueness, increased intra-die hamming distance (HD), greater reliability under supply voltage fluctuations, higher minimum entropy, and substantial reductions in both power and energy consumption. These improvements underscore the potential of memristor-capacitor-based delay structures as a robust and energy-efficient alternative for next-generation secure PUF implementations.