Precise Learning-to-Rank Bug Localization Using Multi-Feature Fusion for Hardware Code
Menglin Yang, Jian Hu · ACM Transactions on Design Automation of Electronic Systems · 2025
Verification is crucial in hardware code development as it ensures the design behaves as intended under all possible conditions, meeting its functional and performance specifications. Bug localization plays a vital role in the verification of hardware code by identifying the precise source of errors detected during simulation, testing, or formal analysis. Dynamic bug localization is a debugging technique that has gained attention in both software and hardware domains. It aims to automatically identify the most likely sources of errors in a design by analyzing the relationship between code coverage (or signal activity) and test outcomes (pass/fail). Despite its promise, DFL in hardware faces several challenges, including the abundance of bug-irrelevant statements, the limited expressiveness of coverage information, and the constrained learning capacity of simple statistical formulas. In this article, we propose Laurel, a l earning-to-r a nk fa u lt localization method for ha r dwar e code using mu l ti-feature fusion. To overcome the existing limitations in DFL, Laurel employs a value dependence graph (VDG) to effectively filter out bug-irrelevant statements. It further enhances semantic feature representation by extracting and fusing multiple features. Finally, a learning-to-rank model is then employed to learn the fused features and compute the suspiciousness score of each statement. We validate the effectiveness of Laurel through comprehensive experiments, comparing it against the state-of-the-art DFL methods on large-scale hardware benchmarks. Results demonstrate that Laurel substantially outperforms all the state-of-the-art DFL methods, achieving an average improvement of 384.6% in Top-1 accuracy for Tartan.