KEM-22: An Efficient Post-Quantum ML-KEM Hardware Accelerator on 22-nm ASIC
Stefano Di Matteo, Ivan Sarno, Emanuele Valea, Sergio Saponara · IEEE Internet of Things Journal · 2025
This paper presents a performant and compact hardware accelerator for the ML-KEM algorithm, compliant with the NIST FIPS 203 specification and implemented in a 22nm ASIC technology. The proposed design supports all three standardized security levels (ML-KEM-512, -768, and -1024) using a unified, parameter-agnostic architecture that avoids logic duplication. The design relies exclusively on SRAM blocks for storage, completely eliminating FIFOs and intermediate buffers, while flip-flops are used only in timing-critical paths to achieve high-frequency operation with minimal area overhead. Among all known ASIC implementations, our architecture achieves the best normalized area-time product across all ML-KEM parameter sets, demonstrating efficiency and scalability, while also delivering the lowest power and energy per operation among state-of-the-art solutions. These results make the proposed design a strong candidate for real-world post-quantum cryptographic deployments on constrained hardware and IoT platforms.