A Novel Nano-Scale Shift Register Architecture with Rest Function Based on Quantum Dots
Li Fu, Saeid Seyedi · IETE Journal of Research · 2025
Quantum-dot cellular automata (QCA) give CMOS technology many advantages, including very low power consumption, increased clock speed, inherent noise immunity and high scalability. As CMOS technology is becoming obsolete due to its lower power efficiency, decreased speeds, susceptibility to noise interference, and lower scalability, QCA nanotechnology is an appropriate substitute. Shift registers are used in QCA's digital circuit and memory cell design. This work proposes new designs for shift registers in nanotechnology in QCA using a D-latch gate configuration distributed across three layers. The multi-layer structure is high-speed with a comparably low cell count, which is low in comparison with conventional designs. In addition, the circuit also provides direct access to outputs and inputs, an element that was greatly overlooked in earlier designs. Another highlight feature of this circuit is a reset pin for shift registers utilized by microprocessors. Something that even the majority of previous designs lacked, this paper proposes a new design for a shift register circuit featuring a reorganize pin. This design is also new in terms of stability, cell count, and area consumed compared with other designs not designed with reset capability. Design performance analysis was done through simulation with the software tool QCADesigner 2.0.3, which demonstrated good characteristics in the dimensions of size and complexity.