Watermarking of Transient Fault‐Detectable IP Designs Using Multivariate HLS Scheduling Based Multimodal Security
Anirban Sengupta, Vishal Chourasia, Nabendu Bhui, Aditya Anshul · IET Computers & Digital Techniques · 2025
Securing reusable hardware intellectual property (IP) cores used in system‐on‐chip (SoC) designs is crucial, due to global design supply chain that may introduce different points of security vulnerability. One of the major threats includes an untrustworthy entity in the SoC design house attempting piracy or falsely claiming ownership of the IP design. Further, owing to the importance of handling transient fault in hardware IP designs, design of fault‐detectable IP designs has become a standard practice in the community. However, these fault‐detectable IP designs are also similarly prone to hardware threats such as IP piracy and false claim of IP ownership. Therefore, robust sturdy countermeasure for fault‐detectable IP designs against such threats is essential. This paper presents a detective countermeasure using proposed novel hardware watermarking methodology for transient fault‐detectable IP designs. The proposed IP watermarking methodology introduces a novel multivariate encoded high‐level synthesis (HLS) scheduling based multimodal security framework. The proposed approach is capable of embedding a robust, unique, and nonreplicable watermark in the HLS register allocation phase of fault‐detectable IP design. The proposed watermarking technique is more robust than the prior watermarking approaches in terms of reduced probability of coincidence (PC; upto ~10 −8 ), stronger tamper tolerance (TT; upto ~10 130 ), and lower watermark decoding probability at 0% design cost overhead.