Investigating Baugh-Wooley multiplier for high-speed digital signal processing applications: A full adder design optimisation approach
Kunjan D. Shinde, Vinaya S. Isarannavar, Chinna V Gowdar, Sushant Jadhav, Vinayak Dalavi, Vallabh Bhat · 2025
Baugh-Wooley multiplication is a classic algorithm used for signed binary multiplication. The technique involves breaking down the multiplication into simpler additions and subtractions, making it well-suited for applications involving large computations like digital filtering, FFT and more. This paper presents optimisation and design of Baugh-Wooley multiplier with focal point being the full adder design, which is an essential building block in the multiplier and critical element for investigation. A conventional and suggested method is introduced to enhance the full adder, and its effects are evaluated on a multiplier implemented on FPGA. Xilinx Design Suite ISE 14.7 is used and multiplier’s performance is captured on Virtex 6 family of FPGA and the device utilisation is reported after post synthesis on XC6VLX75T device, with package FF484, and speed grade of 3. The Baugh-Wooley multiplier, developed using the proposed technique, demonstrates the minimal data path delay, resulting in a high-speed implementation of Baugh-Wooley multiplication.