28 M Weights $\times$ TOPs $/ \mathrm{W}/\text{mm}^{2}$ PCM-Based Analog in-Memory Computing Core with 8 $512 \times 512{}$-Weight Layers in 28 nm FD-SOI CMOS
Marco Pasotti, Riccardo Zurla, J. J. Bertolini Agnoletto, Emanuela Calvetti, Alessio Antolini, Luigi Croce, Giuseppe Desoli, Luca Iannelli, Andrea Lico, R. Vignali, Francesco Zavalloni, Eleonora Franchi Scarselli, Alessandro Cabrini · 2025
In-Memory Computing (IMC) hardware accelerators for Deep Neural Networks (DNNs) require massive quantity of coefficients stored in a single device to limit performance losses in multicore clusters. This aspect, generally neglected by prevalent Figure of Merits (FoM), can be addressed by PhaseChange Memory (PCM) technology thanks to its high density, scalability, non-volatility, and analog storage capability. This paper presents a PCM-based (Ge-rich GST) Analog-IMC macro designed for multilayer, drift-tolerant, and temperature-resilient computations. Fabricated in a 28 nm FD-SOI CMOS process with 4 M -cells array, the accelerator achieves a$<2.14\%$error for Matrix-Vector-Multiplication (MVM) across a wide temperature range (from$-40^{\circ} \mathrm{C}$to 125° C), offering an improvement, with respect to other state-of-the-art hardware accelerators, by a factor 3.5 estimated by means of a FoM defined as No. of Weights$\times \text{TOPS}/\mathrm{W}/\text{mm}^{2}$(or storage-energy efficiency per area).