DFGAS: Exploring the Balance of HW-SW Scheduling through the DFG-Aware Scheme
Tianyu Liu, Zhihua Fan, Wenming Li, Zhen Wang, Yuhang Qiu, Shengzhong Tang, Haibin Wu, Yanhuan Liu, Xiaochun Ye, Dongrui Fan · ACM Transactions on Architecture and Code Optimization · 2025
Coarse-Grained Reconfigurable Architectures (CGRAs) have been regarded as promising spatial computing fabric for the ever-evolving algorithms in multiple domains. However, pure software scheduling cannot compensate for the deficiencies in over-serialization and load imbalancing of these pure static CGRA designs. To address the issues caused by limited hardware flexibility, an in-depth study on the balance between the software and hardware scheduling design of CGRA is needed to achieve more precise, accurate, and adaptive scheduling of dataflow. In this article, we propose DFGAS ( DFG - A ware S cheduling), a dataflow-driven CGRA which provides a comprehensive scheduling approach that encompasses software prediction, runtime adaptive execution, and post-execution refinement. Prior to execution, the TimeStamp prediction algorithm, coupled with the inherent dataflow execution model, enables coarse-grained (block-level) prediction for prioritized transfer and computation on NoC and PEs. During execution, the execution of key dataflow graph (DFG) blocks and edges is accelerated by incorporating a dynamic and adaptive dataflow mechanism. It leverages hardware-software co-design to obtain a holistic view of the entire DFG and continuously self-adaptively optimizes the scheduling process. Furthermore, a complete workflow is implemented, supporting making refinements to the software DFG mapping results. DFGAS represents a scheduling scheme of CGRA that is worth exploring, achieving hardware-software co-design that balances energy efficiency and flexibility. Experiments show that DFGAS achieves 1.35× energy efficiency improvement over a dataflow-driven CGRA and 1.9× energy efficiency improvement over a state-of-the-art pure static CGRA.