Design and Implementation of Approximate Hybrid Floating-Point Multipliers for Signal-Processing Applications
B S Gurucharan, Anwesh Rao, B S Kariyappa · IEEE Access · 2025
Floating-point (FP) multipliers are critical components in high-performance computing systems, particularly in signal processing, graphics, and machine learning applications. However, traditional FP multipliers face challenges in power, area, and latency efficiency. This paper proposes two Approximate Hybrid Floating Point Multipliers (AHFPM1 and AHFPM2), which integrate hybrid Radix-4 and Radix-8 Booth encoding techniques to improve computational efficiency while maintaining high accuracy. AHFPM1 utilizes an approximate 3Y recoding adder to accelerate partial product generation, whereas AHFPM2 employs a novel approximate encoder (AHFPE2) derived through Karnaugh map simplifications to reduce hardware complexity. Both designs selectively apply exact and approximate logic to different sections of the mantissa, enabling precision-aware optimization. Post-layout synthesis using the Sky130HD PDK demonstrates that AHFPM2 achieves up to 61.2% lower power and 55.0% lower Power-Delay Product (PDP) compared to state-of-the-art designs, with minimal loss in accuracy. Experimental evaluation across FP32, FP16, and FP8 formats shows that AHFPMs outperform existing approximate multipliers in terms of Mean Relative Error Distance (MRED), with a maximum error below 2.83% even in ultra-low-precision settings. Application-level validation on JPEG compression and Finite Impulse Response (FIR) filtering confirms functional fidelity and efficiency. These results demonstrate that AHFPM1 and AHFPM2 offer robust trade-offs for low-power, error-resilient FP computing in modern embedded and signal processing systems.