A New Logic BIST for Complete Fault Detection Using Previous Scan-In Bit Dependency
Jongho Park, Sangjun Lee, Jaehyun Kim, H. M. Cho, Nayeun Kim, Sungho Kang · IEEE Access · 2025
As the complexity of System-on-chip (SoC) technology continues to increase, testing to detect faults during manufacturing and in-field operation is essential. This is particularly critical for automotive SoCs that must comply with ISO 26262 functional safety standards. Traditional methods for pseudo random pattern generation have been constrained by inefficient patterns, resulting in limited fault coverage and suboptimal fault detection efficiency. Although deterministic patterns can detect all faults and help ensure circuit integrity, their practical use is often hindered by significant memory overhead. To overcome these drawbacks, a hybrid LBIST pattern generation methodology is proposed, in which pseudo random and deterministic patterns are integrated to achieve full fault coverage while minimizing both test time and memory usage. The proposed method introduces a reconfigurable PRPG-based pattern generation that selectively applies modified pseudo random sequences using prior scan-in bit dependency. Residual faults that are not detected by pseudo random patterns are subsequently detected using deterministic patterns, which are encoded using a flipping-based compression technique. A fixed-length codebook is employed to reduce decoding complexity, measured in terms of the number of codewords while maintaining high encoding efficiency. Through experiments on benchmark circuits, the proposed method has been shown to achieve 100% fault coverage, defined as the ratio of detected to total faults. The number of required patterns has been reduced by 91.67%, and memory overhead has been reduced by 16.80%, measured in terms of storage bits. Furthermore, decoding complexity, expressed as the number of codewords in the codebook, has been reduced by 88.20%. The scalability of the method has also been validated in terms of both memory usage and test time, confirming its effectiveness for large-scale circuits. The proposed method provides a practical and memory-efficient BIST solution that can adapt to constraints in either test time or memory usage, while still achieving 100% fault detection.