Application of Flowcharts in Simulink for VHDL Code Generation
Majid Pakdel · 2025
This chapter presents the application of flowcharts in Simulink for generating VHDL code using HDL Coder, demonstrating its utility in digital system design. Various designs, including a multiplier, GCD calculator, Booth's multiplication algorithm, and an industrial control system, are implemented using Stateflow charts. Each system begins with the initialization of inputs, constants, and intermediate variables using MATLAB fixed-point numeric objects, followed by stepwise implementation of the flowchart as separate states. The chapter details simulation in MATLAB Simulink, verification of functionality through waveform analysis, and subsequent generation of synthesizable VHDL code. Generated VHDL files are then synthesized and implemented using Xilinx Vivado, with RTL schematic analysis and behavioral simulation performed for verification. The methodology emphasizes modularity, clarity, and efficient translation from algorithmic flowcharts to hardware description language code for FPGA-based designs.