Design Low Power Linear Feedback Shift Register for Built-In Self-Test (BIST) Applications
Shubham Badake, Meenakshi Pawar · 2025
With increasing complexity in virtual systems, effective and low-power testing methods are essential for Built-In Self-Test (BIST) applications because they allow on-chip testing, reducing the need for external hardware while improving reliability. BIST widely utilizes linear feedback shift registers (LFSRs), a core component, to generate pseudo-random test patterns. However, conventional LFSRs consume significant power, making them unsuitable for modern low-power applications like IoT and mobile devices, because the linear feedback shift register (LFSR) uses a large number of flip-flops that consume maximum power. To overcome this issue, this research focuses on designing a low-power LFSR optimized for BIST applications using VLSI techniques. By using bi-enabled pulsed latches in GPDK045 technology, this research work will be carried out on the design of a low-power LFSR, which reduces output power for generating a test pattern circuit and also reduces leakage current. The proposed LFSR design is implemented in the Cadence Virtuoso tool with the available CMOS libraries. Based on the implementation result, its power consumption is$150 \mu\ \mathrm{W}$at a 100 MHz clock frequency with VDD$=5\ \mathrm{V}$. For reduced power, the bi-enabled pulsed has taken the place of the D-flip-flop. The proposed design offers an effective solution for self-testing, enhancing the overall reliability and sustainability of digital systems.