Design and Implementation of Low Power Parallel Transposed FIR Filter Using Modified Gate Diffusion Input Technique
K Murugesan, M.E. Prathika · 2025
FIR filters serves a fundamental part in Digital Signal Processing (DSP), offering accurate frequency control and stability across a wide range of applications. This paper proposes a parallel transposed FIR filter structure utilizing Modified Gate Diffusion Input Technique to implement the arithmetic blocks of the filter. This work addresses the dual challenges of attaining high performance and energy efficiency in parallel transposed FIR filter designs. The MGDI implementation of AND, OR, and XOR logic results in fewer transistor counts than conventional CMOS logic implementations. In order to increase the performance and energy efficiency of the filter concerning the transistor count and power consumption, this paper advocates the utilization of the proposed MGDI technique circuit within the design of the parallel transposed FIR filter. Dadda multiplier and Ripple Carry Adder are incorporated in our proposed filter design. The proposed filter structure is developed and implemented in the Cadence Virtuoso environment using 45nm technology. The scheme of paper is as follows: design and optimization of FIR filter architecture, and then to analyze system performance.