Design and Development of Cost Optimized Quantum Binary-Coded Decimal Adder using Reversible Logic Gates
Parna Kundu, Mousom Chatterjee, Susmita Biswas, Himadri Sekhar Das, Santanu Mishra, Swarnajit Bhattacharya, Sudipta Banerjee, Aritra Bhowmik, Heranmoy Maity · ES General · 2025
Within this paper, the authors introduce a new cost optimized quantum Binary-Coded Decimal (BCD) adder circuit that utilizes reversible gates as its building blocks. The newly proposed quantum BCD adder is specifically constructed with the inclusion of double Peres gates (DPG), Peres gates (PG), BJN gates, Feynman gates (FG), and reversible NOT gates. To bring this idea to life, we undertook the design and implementation of the proposed circuit using the Qiskit simulator provided by the IBM Quantum Computing lab. Our evaluation of the newly optimized BCD adder circuit yielded the following metrics, the quantum cost of 47, the constant input of 8, garbage output of 12, and a delay of 10. When compared to previously reported results, we observed significant improvements in various aspects, with a 25.39% reduction in quantum cost, a 28.57% decrease in constant input, and a 36.84% reduction in garbage output.