VLSI Design Course with FPGA Implementation of Pipelined RISC-V Processor
Siu Hong Loh, Gui Ye Tan, Jia Jia Sim · 2025
This study presents the design and FPGA implementation of as-stage pipelined RISC-V processor using System Verilog HDL. The processor leverages RISC-V's open-source., flexible instruction set and pipeline technology to enhance performance. Key modules., including the controller., ALU., datapath., memory., hazard unit., and pipeline registers., are implemented to ensure efficient execution. The design is verified through testbenches and simulations in ModeISim-Intel® FPGAs Standard Edition., followed by FPGA synthesis on an Altera DE1-SoC board. This work integrates modern RISC-V architecture with rigorous verification., aligning with advancements in processor design. The paper outlines a methodology that may be used in undergraduate VLSI design courses.