RCS-SAR: A 12-Bit 20MS/S Secure ADC with Random Capacitor Switching Against Power Side-Channel Attacks
Jixiang Zhang, Shipeng Zhang, Jiaji He, Mao Ye · 2025
Analog-to-digital converters (ADCs) exhibit a hardware security vulnerability that allows attackers to steal sensitive output information by observing current waveforms from exposed power supply pins. This paper presents a successive approximation register (SAR) ADC that employs a mechanism of random capacitor switching to the$V_{C M}$reference voltage. This approach effectively encrypts the current waveform, providing protection against power side-channel attacks (PSCA). A 12-bit, 20 MS/s secure SAR ADC using 55-nm CMOS validates the proposed design. It encrypts the reference current waveform, reducing the amplitude of the current signal from −46 dB to −81 dB and decreasing the signal-to-noise ratio (SNDR) of current by 4 bits. In protected mode, the Nyquist spurious-free dynamic range (SFDR) and SNDR at 20 MS/s were simulated at 90.4 dB and 70.4 dB, resulting in a figure of merit (FoM) of 22.1 fJ/conv.-step.