A Self-Organizing Linked Storage Architecture With Dynamic Partition Achieving High Capacity Utilization
Siwei Xiang, Yu Gao, Yishuo Meng, Jianfei Wang, Ge Li, Zhijie Lin, Chen Yang · IEEE Transactions on Circuits & Systems II Express Briefs · 2025
This paper proposes a self-organizing linked on-chip (SLO) storage architecture and a coarse-grained management scheme to achieve high storage capacity utilization (SCU), low off-chip data traffic, efficient access, and high performance. On the one hand, the SLO storage architecture can be dynamically partitioned into uneven In-/Out-/Weight-Buffer to improve SCU up to 93.14% and reduce off-chip data traffic for each layer. On the other hand, the management scheme based on singly linked lists with 5.3% hardware overhead is proposed to enable efficient access by a dynamic weight-preloading strategy and a two-stage access pattern. Leveraging these innovations, a reconfigurable SLO-based accelerator with a dual buffer exchanging structure is designed. Compared with state-of-the-art (SOTA) works, this accelerator can increase SCU by 1.29×-2.33× and improve DSP efficiency by up to 3.81× on FPGA platforms while achieving 1.44×-5.06× higher area efficiency on ASIC implementations.