An Optimized Reversible Multiplier with Sklansky Adder for Next-Generation ALUs
Rishu Yadav, Nagendra Kushwaha, Sandeep Mishra, Ashish Ranjan Kumar · IETE Journal of Research · 2025
The rising demand for high-performance and low-power consumption in modern computing devices is making the method of Arithmetic Logic Units (ALUs) a critical area of focus. This paper introduces a novel reversible multiplier architecture integrated with a Sklansky adder, specifically designed to address the challenges of modern ALUs, such as power reduction, low propagation delay and efficient resource utilization. By leveraging the parallel prefix efficiency of the Sklansky adder and the inherent power-saving capabilities of reversible logic, the proposed architecture achieves superior performance metrics. Synthesized and evaluated on the ARTIX-7 FPGA (XC7a35tcpg236-1) using VHDL in Xilinx Vivado, the design demonstrates a propagation delay of 6.458 ns, a power consumption of 26.442 µW, and a power-delay product (PDP) of 170.762 fJ. These results significantly outperform existing designs, highlighting the architecture’s scalability and suitability for compact, low-power System-on-Chip (SoC) applications. This work sets a new benchmark in reversible logic-based ALU design, paving the way for advanced, energy-efficient computing platforms.