An Area-Efficient ChaCha20 Hardware Accelerator Design for Secure and Real-Time Communication in CAVs
Myeongjin Kwak, Tae Hee Lee, Do Hoon Lee, Tae-Hyoung Kim, Yongtae Kim · 2025
This paper proposes a hardware implementation of the ChaCha20 stream cipher optimized for secure and low-latency communication in resource-constrained environments, such as connected and automated vehicles (CAVs). To reduce latency and improve throughput, QuarterRound operations are unrolled into combinational logic. Three hardware architectures with different per-cycle QuarterRound computation capacities are designed and implemented in Verilog HDL, then synthesized using$65-\text{nm}$CMOS technology. Experimental results show that the proposed designs achieve a balanced trade-off between area, power, and performance. CR-2, in particular, offers a well-rounded configuration by achieving 7.44 Gbps at 214.59 MHz while maintaining a reasonable balance across all metrics.