MPSoC based pipelined architecture signal processing of SSR
Ramyakusuma Sunkara, Shikha Pallavi, Salman Baig, Reep Khanikar, Arbind Kumar Singh · 2025
In this paper, the signal processing algorithms are designed with an optimized approach to reduce the processing time of Secondary Surveillance Radar(SSR) replies. In the traditional approach, these signal processing algorithms are developed using C language in processor. To improve processing time, a novel method is proposed that enables the optimised way of pipeline processing of the replies. These algorithms are efficiently implemented in the MPSoC FPGA. In this design, the processing time has reduced by 30-40% compared with the processor-based traditional methods.