RTL to GDSII: Design and Physical Implementation of a 32-bit RISC-V Floating-Point Co-Processor Using Verilog and Cadence Tools
Chandrashekar M Patil, A Geethashree, R Srinivasa, R Rakshith Yadav, S Ajay H, S Dravid · 2025
The paper presents the RTL-to-GDSII implementation of a 32-bit RISC-V floating-point co-processor in Verilog and standard Cadence tools. The co-processor adheres to IEEE 754 on all single-precision arithmetic operations to speed up the processing of floating-point calculations for embedded systems. The design methodology includes architectural modelling, RTL design, synthesis, place-and-route (PnR), and tapeout level sign-off verification. A systematic methodology was pursued for achieving optimal trade-off between performance, area, and power. The final implementation is realized in 90 nmCMOS technology, achieving a maximum frequency of 210 MHz and consuming 38.5 mW in normal conditions. This shows the effectiveness of merging the RISC-V modular architecture with floating-point capabilities in a low-power domain.