Comparative Study of Multiplier Techniques for FIR Filters in Real-Time Multimedia Applications
M. Rajesh, V Anuraj, Dhandapani Vaithiyanathan, Manish Kumar Verma, Baljit Kaur, Preeti Verma · 2025
This paper presents an in-depth comparative analysis of various multiplier architectures for Finite Impulse Response (FIR) filter implementation in real-time multimedia applications. The study evaluates six prominent multiplier designs—Array, Wallace Tree, Baugh-Wooley, Modified Booth, Baugh-Wooley with Wallace Array (BA-WA), and Dadda—targeted on a Xilinx Artix-7 FPGA using the Vivado 2024.2 toolchain. Each architecture is analyzed across multiple operand widths (8-bit, 16-bit, and 32-bit) with respect to key performance metrics, including slice utilization, critical path delay, power consumption, Area-Delay Product (ADP), and Energy-Delay Product (EDP). Among the evaluated architectures, the Dadda multiplier demonstrates the best overall efficiency, achieving significant reductions in both area and delay while maintaining low power consumption, especially for high-precision operations. The results confirm that Dadda and BA-WA multipliers are highly suitable for resource-constrained and high-performance digital signal processing (DSP) applications, offering a balanced trade-off between speed, power, and hardware resource usage.