An empirical study of parallel SGD Algorithms on RISC-V multicore processors
Shaojie Liang, Anwen Huang, Deheng Yang, Qiong Li · IET conference proceedings. · 2025
Stochastic Gradient Descent (SGD) represents one of the most prevalent optimization algorithms in machine learning. To accelerate the SGD algorithm, a series of parallel SGD algorithms have been proposed. Due to its inherent robustness, parallel SGD is frequently employed to mitigate inefficiencies by accessing and updating the shared model parameters in a lock-free manner. Recently, RISC-V has received widespread attention from the academic and industrial communities due to its characteristics of simplicity, open source, and customization. With the successive advent of RISC-V multicore processors and their gradual application in the field of high-performance computing, the adaptation of various machine learning algorithms on RISC-V is an area worthy of attention. In this paper, we conduct a quantitative analysis of the performance of parallel SGD algorithms on RISC-V multicore processors at both the software and hardware levels. We utilize RISC-V instruction-level and architecture-level simulators to identify bottlenecks in the design of parallel SGD algorithms and cache coherence protocols. This provides an experimental reference for the co-optimization of software and hardware design for SGD algorithms on RISC-V multicore processors.