Efficient Fault-Detection Architectures for Barrett Reduction and Multiplication in Classical and Post-Quantum Cryptographic Systems
Saeed Aghapour, Kiarash Sedghighadikolaei, Attila A. Yavuz, Bechir Hamdaoui, Mehran Mozaffari Kermani · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2025
Barrett modular reduction and multiplication are essential primitives for efficient modular computation in cryptographic schemes, including post-quantum standards such as machine learning (ML) key encapsulation mechanism (KEM) and ML-digital signature algorithm (DSA). To protect against faults that compromise correctness and security, we introduce the first efficient fault-detection mechanisms tailored to these operations. For modular reduction, we leverage word-based representations with compact word-sum checks that exploit algebraic input-output relations to ensure computational integrity. For modular multiplication, we adopt a tunable hybrid strategy: early stages apply word-sum checks, while later stages use partial recomputation with encoded inputs, providing robust protection against injected faults. Formal analysis, fault-injection simulations, and hardware/software implementations show that our methods detect a wide range of faults with minimal performance and area overhead. Evaluation results demonstrate overheads of 3.43% and 7.15% for 512-bit and 1024-bit inputs in modular reduction, and 26.47% and 27.22% for 2048-bit inputs in modular multiplication in the number of clock cycles in software. Moreover, in hardware, we observed reasonable overheads: less than 27.5% in area and 2.1% in delay for modular reduction, and less than 23.5% in area and 16.2% in delay for modular multiplication. These results confirm the practicality of our methods for secure yet efficient integration.