Achieving Low Serving Latency in DPDK-Applied Systems at Multi-Tenant Edge Clouds
Yuki Tsujimoto, Yuki Sato, Kenichi Yasukata, Kenta Ishiguro, Kenji Kono · IEICE Transactions on Information and Systems · 2025
This paper explores a practical means to employ Data Plane Development Kit (DPDK), a kernel-bypassing framework for packet processing, in resource-limited multi-tenant edge data centers. Traditional virtual CPU (vCPU) schedulers are not compatible with the event detection model of DPDK, because each DPDK-applied VM (virtual machine) monopolizes one physical CPU (pCPU) for NIC register polling. Toward edge data center providers, this paper presents a new vCPU scheduling policy named Polling vCPU Consolidation (PvCC). PvCC enables DPDK-applied VMs to be consolidated on dedicated pCPUs by adopting microsecond-scale time slices. Along with this, PvCC provides vCPU scaling API that enables to scale up/down vCPUs of VMs at runtime. Our experiments show that PvCC allows consolidated DPDK-applied VMs to achieve low serving latencies, and our vCPU scaling API allows us to adjust CPU resource assignment according to the incoming request rate. It also enables to assign spare pCPUs to VMs executing non-latency-sensitive tasks.