Read disturb mechanisms and solutions in 3D NAND Flash
Jing Zhang, Zhong Ji, Yongwang Zhou, Yang An, Qihao Liu, Zhaogui Zeng, Bojie Lou · 2025
As big data, cloud computing, and artificial intelligence develop rapidly, the demands for high-performance storage chips have become increasingly stringent. NAND Flash, as a prominent integrated solution for high-capacity non-volatile data storage, has got significant attention. To overcome the capacity limitations of 2D NAND Flash, 3D NAND Flash technology emerged. However, the vertical stacking architecture of the 3D NAND Flash exacerbates read disturb issues. Specifically, when the transistor on the selected wordline (WL) performs a read operation, the transistors on the unseleted WLs on the same bitline experience soft programming due to the application of pass voltages. Repeated read operations may induce threshold voltage shifts in these adjacent cells, leading to bit flips and read errors, thereby degrading the reliability of NAND Flash. To solve read disturb problem, various solutions have been proposed, including read retry, read reclaim, and advanced buffer management technologies. This review comprehensively discusses the mechanisms of read disturb, and the solutions to read disturb and future directions.