Design Consideration of Scalable and Adaptive FPGA-Based Convolutional Layer Accelerator
Jirayu Peetakul, Sivapong Nilwong, Natthorn Chuayphan, Supaluk Prapan, Onanong Sukjai · 2025
This paper presents a design consideration of scalable and adaptive FPGA-based convolutional layer accelerator (CLA) optimized for inference. The architecture enables efficient parallel processing across multiple pods, each handling different tensor channels with shared IFMAPs. It dynamically scales processing elements (PEs) at runtime to maximize resource utilization. The system adapts pod and PE activation based on CNN layer requirements, optimizing resource allocation and performance. This design offers a flexible foundation for accelerating convolutional operations in FPGA-based implementations.