Pipelined Implementation of Secure Hash Algorithm on FPGA for Enhanced Performance
Ismail Mchichou, Mohamed Amine Tahiri, Rabab Ouchker, Hicham Amakdouf, Hassan Qjidaa · 2025
This paper presents the implementation and opti-mization of the SHA-256 algorithm on an FPGA platform, specif-ically on the Xilinx Artix-4 DDR board. The main objective is to enhance the performance of hashing operations, which are crucial for real-time applications such as Bitcoin mining. A pipelined architecture was adopted to enable more efficient management of message blocks, thus reducing computation time while optimizing the use of available resources. Experimental results demonstrate a significant reduction in execution time, from 2.74 μs to 1.43 μs, representing an improvement of approximately 48%. Although a slight increase in FPGA resource utilization was observed due to the introduced parallelism, overall energy consumption has slightly increased. This work highlights the potential of FPGA platforms in accelerating cryptographic operations in systems that require both high performance and resource optimization.