Implementation of Bilateral Filter Architecture on FPGA for Image Denoising
M S Anakha, Nikhil M, V R Adersh · 2025
The bilateral filter performs better in edge preservation and noise suppression. The work proves that such a new approximate method can be used efficiently in designing reconfigurable denoising filters, producing image quality close to that of exact software counterparts. This implementation contributes to the reduction in the usage of hardware resources and power. The proposed hardware architecture is implemented on Spartan 7 Field Programmable Gate Array (FPGA) board. Apart from image denoising, peak signal-to-noise ratio (PSNR) and structural similarity index (SSIM) are also computed and comparison is made between the PSNR and SSIM values calculated by the implementation of bilateral filter in hardware and software by using verilog as well as python programming. Also, power consumption of the architecture is reduced by implementing a flip flop based clock gating. To verify the effectiveness, a Gaussian filter is implemented for comparison with the bilateral filter. for The PSNR measure in Vivado is 36.03 dB compared to 31.17 dB from the Python implementation, which suggests the FPGA-based processing in Vivado generates less noise and improved image reconstruction. Similarly, the SSIM value of Vivado is 0.823, as opposed to 0.621 in Python, indicating that the Vivado implementation maintains better structural image details.