High Performance 64-bit MAC Unit for DSP Applications
Indupuru Thrivikrama Reddy, B. Suresha, S. Ravi · 2025
This increasingly growing requirement for effective digital signal processing has created an immediate need for optimizing arithmetic components. A new methodology of designing the 64-bit MAC unit that is notably evident in providing a significant amount of power savings without compromising on the level of performance achieved. The proposed architecture makes use of the DADDA algorithm in the multiplication stage. A new hybrid accumulator, that brings together carry look-ahead and carry select adder's benefits, is provided as support. The design was realized using Verilog-HDL, and extensive synthesis on two widely recognized industry platforms-Cadence's Genus tool with 45nm CMOS technology and Synopsys tools with 14nm FinFET technology. Findings of the experiment indicate the best optimal position the adopted approach meets between performance and energy-efficiency. The research introduces the field of energy-effective computing, particularly useful when devices are dependent on powered or high-performance digital signal-processing applications, which is major power consumption limitation. Other notable limitations include the huge number of cells and cell area that is manyfold higher than the previous works