Performance Analysis of a 16-Bit Dadda Multiplier with Multiplexer Based Approximate Adders
N. Udaya Kumar, K. Bala Sindhuri, G.V.S.Padma Rao, Polamuri Santhi Priyanka · 2025
Multiplication is a fundamental operation in digital systems, especially in domains like Digital Signal Processing (DSP), Machine Learning, and VLSI design. This paper presents the performance analysis of a 16-bit Dadda multiplier integrated with multiplexer-based approximate adders to address design trade-offs in power, area, and delay. Leveraging the Divide and Conquer technique, the proposed architecture incorporates approximate computing principles to reduce computational complexity. The system is implemented in Verilog HDL and synthesized using Vivado 2023.2 and Cadence tools. Results reveal that the design achieves considerable improvements in power and area efficiency with marginal accuracy degradation. These findings validate the effectiveness of integrating approximate computing in multiplier design to meet the demands of energyefficient digital circuits.