Implementation and Comparison of Approximate Parallel Prefix Adders for Enhanced Performance in Three Operand Binary Addition
Aneena Babu, Hanna Mathew · 2025
The area of digital system design is evolving, hence the significance of high speed arithmetic operation is also increasing. The applications like cryptography, signal processing, high-performance computing require faster and efficient adder architectures. Since the existing adders are exhibiting delay mostly in the case of carry propagation, Parallel Prefix Adders can be used for reduced delays even in cases involving large number of bits arithmetic operations. The Approximate Parallel Prefix Adder technique utilizes the approximation method for more efficient architectures. In this work, five basic topologies of approximate parallel prefix adders are compared for the performance enhancement in three operand binary addition. The bit sizes 16 bits, 32 bits, 64 bits of the adder topologies are implemented to obtain the comparative analysis related to different performance parameters. It is simulated and implemented on Vivado Design Suite and is prototyped on Nexys 4 Artix- 7 FPGA Board for the on-chip functional verification.