Optimizing SPHINCS+ for Low-Power Devices
Alexander Magyari, Yuhua Chen · Electronics · 2025
Different optimization techniques for the SHAKE variant of SPHINCS+ are explored on an FPGA with the means to find a power-efficient model for resource-constrained devices. This work explores multiple hashing implementations, such as registering inputs and directly feeding data to hashing units, as well as different variations in hashing permutations per clock cycle. The design is evaluated based on resource requirements, the signature generation rate, and both static and active power consumption. This design shows a decrease in energy consumed per signature by 20% to 30% compared to other state-of-the-art SPHINCS+ implementations, while only using 12–14k lookup tables (LUTs), depending on the SPHINCS+ variant. Moreover, an amendment is proposed to the SPHINCS+ specification that allows for decreased processing time and memory consumption while maintaining the security level and non-deterministic properties. This is accomplished by rearranging the inputs in the random oracle model.